1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors and used for generating a different type of strain in channel regions of different transistor types.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies for advanced semiconductor devices are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
During the formation of the two types of stressed layers, conventional techniques, also referred to as dual stress liner approaches, may suffer from reduced efficiency when device dimensions are increasingly scaled by using the 45 nm technology and even further advanced approaches, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a top view of a portion of a semiconductor device 100, which may include a plurality of transistor elements 150 that may be provided in a device region having a high packing density. In sophisticated semiconductor devices, certain device areas may require a high density of individual transistor elements, for instance in memory areas and the like, to provide a high degree of information density and the like. In this case, neighboring transistor elements, such as the transistors 150, may have a lateral distance of approximately several hundred nanometers and less, depending on the technology standard under consideration. For example, each of the transistors 150 may comprise an “active” region, which is to be understood as a semiconductor region containing appropriate dopant species so as to form corresponding PN junctions and a channel region required for the transistor function. Furthermore, a gate electrode structure 152 is typically provided and extends along a transistor width direction, indicated as W, wherein the gate electrode structures 152 may typically extend above a corresponding isolation region, which may typically laterally enclose the corresponding active regions 151. The gate electrode structures 152 may be correlated with a corresponding channel length L, which is an important characteristic of the transistors 150 that determines the overall performance thereof. For example, a channel length of 40 nm and less may be used in sophisticated semiconductor devices, thereby also resulting in a corresponding reduced lateral distance between neighboring transistors in densely packed device areas. Furthermore, in the manufacturing stage shown, the transistors 150 may be covered by a stress-inducing dielectric layer 130 (FIG. 1b), which may have an internal stress level for modifying the lattice structure in the channel regions of the transistors 150, thereby increasing charge carrier mobility therein, which in turn may result in enhanced transistor performance, as previously explained.
FIG. 1b schematically illustrates a cross-sectional view of the semiconductor device 100 of FIG. 1a. As illustrated, the semiconductor device 100 may comprise a substrate 101, above which is formed a semiconductor layer 102. For example, the substrate 101, in combination with the semiconductor layer 102, which is typically provided as a silicon semiconductor layer, may define a silicon-on-insulator (SOI) configuration if a buried insulating layer (not shown) is positioned between the substrate 101 and the semiconductor layer 102. Moreover, an isolation structure 103 is formed in the semiconductor layer 102 and separates the active regions 151 of the transistors 150, if required. In other cases, the transistors 150 may be formed in the same active region without providing the isolation structure 103. Typically, the isolation structure 103 is provided as a shallow trench isolation and extends down to a specified depth in the semiconductor layer 102, for instance down to a buried insulating layer if an SOI configuration is considered. Furthermore, the gate electrode structures 152 are formed above the corresponding active regions 151 wherein, in the manufacturing stage shown, each of the gate electrode structures 152 may comprise a gate insulation layer 152C formed on a portion of the active region 151 and separating a gate electrode material 152B from a channel region 154. The gate insulation layer 152C may be comprised of any appropriate material, such as a silicon dioxide based material, while the gate electrode material 152B may be provided in the form of a polysilicon material and the like. Furthermore, a metal-containing material, such as a metal silicide 152A, may be formed in and on the gate electrode material 152B. Additionally, a sidewall spacer structure 152D is formed on sidewalls of the gate electrode material 152B. As previously indicated, lateral extension of the gate electrode material 152B in FIG. 1b may represent the corresponding channel length of the transistors 150 and may be approximately 40 nm and less in sophisticated applications. The corresponding length of the gate electrode material 152B may be correlated with a length of the channel region 154, which is determined by the distance of drain and source regions 153 formed in the corresponding active regions 151. Moreover, a metal silicide region 155 may be provided in an upper portion of the drain and source regions 153 and may be offset from the channel region 154 by a distance that may be substantially determined by a width of the spacer structure 152D. Moreover, the stress-inducing material layer 130 is formed above the transistors 150 and has a high internal stress level so as to induce a desired type of strain in the channel regions 154, such as compressive or tensile strain.
Typically, the semiconductor device 100 as shown in FIGS. 1a-1b may be formed on the basis of the following conventional process strategies. After forming the isolation structure 103, for example using sophisticated lithography, etch, deposition and planarization techniques, the basic conductivity type in the active regions 151 may be defined by an appropriate implantation sequence. For example, the transistors 150 may represent N-channel transistors or P-channel transistors. Thereafter, appropriate materials for the gate insulation layer 152C and the gate electrode material 152B may be provided, which may be accomplished on the basis of sophisticated oxidation and/or deposition and surface treatment techniques for forming material of the gate insulation layer 152C. Next, a gate electrode material is deposited, for instance in the form of a polysilicon material, possibly in combination with any cap materials, anti-reflective coating (ARC) materials and the like, as may be required for the further processing of the device 100. Subsequently, sophisticated lithography techniques are applied to form an appropriate etch mask for patterning the gate electrode material. Thereafter, the dopant profile for the drain and source regions 153 may be defined in combination with appropriate intermediate manufacturing stages of the spacer structure 152D, which, in combination with the gate electrode material 152B, may act as an implantation mask. After final anneal processes for activating the dopant species and re-crystallizing implantation-induced damage, the metal silicide regions 155 and 152A are formed, thereby completing the basic transistor configuration. Next, the stress-inducing material 130 may be deposited, for instance in combination with an appropriate etch stop material (not shown), if further patterning of the material 130 according to well-established dual stress liner approaches is required. The material 130 may be provided as a silicon nitride material which may be deposited with high internal tensile or compressive stress levels, as previously explained.
In sophisticated device geometries, the thickness of the layer 130 has to be adapted to the resulting surface topography, thereby affecting the overall efficiency of the strain-inducing mechanism provided by the stress-inducing layer 130. In addition, in densely packed device regions in which the layer 130 may act on neighboring transistors, such as the transistors 150, the performance enhancing effect of the layer 130 may be significantly less than expected. It is assumed that the reduced strain-inducing efficiency may be caused by the close proximity of the transistors 150 and the corresponding interaction of the internal stress level of the layer 130 on both transistors 150. Consequently, the sophisticated surface topography in densely packed device regions may result in a significantly reduced strain-inducing efficiency, thereby providing a significantly less pronounced performance gain, although stress-inducing materials of high internal stress levels may be used.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.